Huawei LogicFolding: 3D Chips Without EUV

What did Huawei announce at IEEE ISCAS 2026?

On May 25, 2026, He Tingbo—president of Huawei's semiconductor department and a board member of the group—presented two linked ideas at the IEEE ISCAS conference in Shanghai. The first is the Tau (τ) scaling law, a proposed replacement for Moore's Law that optimizes signal propagation delay across the full computing stack rather than shrinking the physical etching pitch. The second is LogicFolding, a 3D architecture that stacks active logic layers vertically to increase transistor density without relying on ASML's EUV lithography machines.

Huawei claims LogicFolding produces a transistor density 55% higher than conventional planar designs. That figure has not been independently verified as of May 25, 2026, according to ActuIA's reporting on the announcement.

What does "1.4 nm equivalent" actually mean?

This is the most important distinction in the announcement. Huawei's 2031 target is an architectural density equivalent to a 1.4 nm node—achieved by counting transistors across multiple stacked vertical layers projected onto the same silicon footprint. It is not a claim that Huawei can physically etch patterns at 1.4 nm resolution.

Paul Triolo, technology lead for Asia and the Americas at DGA Group, told CNBC on May 25, 2026: "a stacked or folded design can produce effective density gains, but it does not mean Huawei has solved the full process, yield, power, thermal, and device-performance problems associated with true 1.4 nm-class manufacturing." No public data on yield, power consumption, or thermal performance accompanied the announcement.

Is 3D stacking unique to Huawei?

No. As ActuIA notes, the 3D stacking of active layers is not an innovation exclusive to Huawei. Several Western and Korean foundries have pursued similar approaches. What Huawei is doing is applying 3D stacking specifically as a workaround for its lack of access to EUV equipment—equipment that TSMC provided until 2020, before U.S. export controls cut off that supply chain.

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According to a report from the Information Technology and Innovation Foundation published in October 2025, U.S. export controls have paradoxically pushed Huawei to independently rebuild competencies it previously sourced externally.

What does Huawei's roadmap look like?

Here's what we know so far from the sources about Huawei's confirmed milestones:

• Past six years: Huawei claims to have designed and mass-produced 381 chips based on the τ scaling principle. This is self-declared and has not received external academic validation as of May 25, 2026.
• Fall 2026: First Kirin chips featuring LogicFolding are expected to ship.
• 2030: The LogicFolding roadmap is projected to extend to Ascend chips—Huawei's domestic substitutes for Nvidia training GPUs banned from export to China.
• 2031: Target density equivalent to a 1.4 nm process through 3D architectural design. Large core frequencies are projected to reach 5 GHz.

The day of the announcement, shares of Chinese foundry SMIC jumped 7.6% in Hong Kong, according to CNBC. For more on how chip supply constraints are reshaping the market, see our coverage of TSMC pricing strategy and Nvidia's China sales.

What did SemiAnalysis find in the Kirin 9030 teardown?

Separately, Dylan Patel's SemiAnalysis released the first public teardown report from its STEEL Lab, targeting the Kirin 9030 Pro—the chip inside the Huawei Mate 80 Pro, manufactured on SMIC's N+3 process node.

The headline finding: SMIC N+3 achieves a transistor density of 113.4 MTr/mm², slightly above TSMC N6's 107.7 MTr/mm². Cell height dropped from 252 nm on N+2 to 228 nm, and contacted gate pitch shrank from 63 nm to 57 nm. SMIC accomplished this using only DUV lithography—no EUV.

As Odaily's analysis of the SemiAnalysis report explains, the cost is steep. SMIC's M0 layer uses Self-Aligned Quadruple Patterning (SAQP)—processing a single mask pattern four times to achieve finer lines. TSMC N6 only requires Self-Aligned Double Patterning (SADP) for the same layer. More masks, tighter overlay accuracy, more process steps, and higher yield risk all follow. SemiAnalysis itself called the headline metal pitch figure—32.5 nm, finer than Intel 18A's 36 nm—a "cherry picked metric."

How does the Kirin 9030's performance compare?

The CPU gap is notable. The TaiShan Prime core's instructions-per-clock sits at roughly the level of Arm's Cortex-X2, a 2021 design. SemiAnalysis cited a 2.7× IPC gap versus Apple's latest M5.

This performance picture connects directly to the strategic logic behind LogicFolding. Huawei cannot close the gap through lithography alone, which is why the 3D stacking roadmap matters for its Ascend chip ambitions as a domestic Nvidia alternative.

What broader shifts does the SemiAnalysis report identify?

The teardown report notes several ripple effects from export controls on China's chip ecosystem. SMIC's process knowledge is diffusing to Hua Hong. CXMT DRAM has been integrated into Huawei's flagship supply chain. And domestic EDA tools are being co-optimized for 3D stacking. These are structural shifts, not one-off workarounds—a dynamic also visible in how U.S. policy has shaped AI infrastructure competition more broadly.

The next concrete milestone on the public record: the first Kirin chips featuring LogicFolding are expected in fall 2026.