# Intel EMIB Targets TSMC CoWoS in AI Packaging

> Source: [https://icharles.com/articles/intel-emib-tsmc-cowos-ai-packaging](https://icharles.com/articles/intel-emib-tsmc-cowos-ai-packaging) (canonical)
> Author: iCharles News — iCharles, https://icharles.com
> Published: 2026-07-03

## TL;DR

Intel's EMIB (Embedded Multi-die Interconnect Bridge) packaging technology is being evaluated for Nvidia's next-generation chip architecture, according to multiple reports. In March 2026, Intel CFO David Zinsner told the Morgan Stanley conference that Intel's packaging business was shaping up to be significantly larger than originally anticipated. The development puts Intel Foundry in direct competition with TSMC's CoWoS, which currently packages most high-performance AI chips including Nvidia's GPUs and AMD's accelerators.

## What is Intel EMIB and why does it matter for AI chips?

**EMIB** is Intel's Embedded Multi-die Interconnect Bridge, a packaging technology that connects multiple chips inside a single package. It is now being evaluated as an alternative to TSMC's dominant CoWoS packaging for Nvidia's next-generation chip architecture, [according to reporting from Damn Ang's Substack](https://damnang2.substack.com/p/emib-intel-foundrys-best-hope).

In March 2026, Intel CFO David Zinsner told the Morgan Stanley conference that the packaging business was shaping up to be significantly larger than originally anticipated.

## Why has advanced packaging become so critical?

The semiconductor industry's bottleneck has shifted. For a long time, performance gains came from shrinking transistors. That's no longer the whole story.

Today, what matters is how fast and efficiently you can connect multiple chips inside a single package. As [chipstrat.com explains](https://www.chipstrat.com/p/advanced-packaging-intels-emib-vs), the packaging itself is now becoming the dominant cost variable in the bill of materials for AI accelerators.

The root cause is the **reticle limit**: the largest area a lithography stepper can pattern in a single exposure, roughly 26 mm × 33 mm, or about 858 mm². Nvidia's H100 was already pushing that ceiling. Blackwell broke through it by stitching two reticle-sized compute dies together. Once you need more than one die, you need advanced packaging.

This pressure on [AI memory chip](/articles/ai-memory-chip-shortage-2026) supply chains extends well beyond wafers and transistors.

## What is TSMC's CoWoS and why is supply tight?

**CoWoS** (Chip on Wafer on Substrate) is TSMC's family of advanced packaging technologies. It is the dominant method for packaging high-performance AI chips today. Nvidia's AI GPUs, AMD's accelerators, and Broadcom's custom ASICs are all packaged using CoWoS.

The problem is supply. By industry estimates, Nvidia absorbs a substantial portion of available CoWoS capacity, leaving other customers struggling to secure allocation.

CoWoS comes in several variants — CoWoS-S, CoWoS-R, and CoWoS-L. Chipstrat also notes chatter about TSMC leaning on panel-level packaging (CoPoS) to handle Nvidia's Rubin Ultra, which allegedly requires four reticle-sized compute dies stitched together into one package. There are also reported rumors of a warpage problem on that four-die package, with a possible fallback to a 2+2 configuration.

## How does Intel EMIB compare to TSMC CoWoS?

Here's what we know so far from the sources on the two approaches:

| Feature | TSMC CoWoS | Intel EMIB |
|---|---|---|
| Current AI chip customers | Nvidia, AMD, Broadcom | Being evaluated for Nvidia next-gen |
| Supply status | Constrained; Nvidia absorbs large share | Described as significantly larger opportunity than anticipated |
| Packaging family variants | CoWoS-S, CoWoS-R, CoWoS-L, CoPoS | EMIB (Embedded Multi-die Interconnect Bridge) |
| Industry position | Dominant | Challenger |

Intel CFO David Zinsner's March 2026 comments at the Morgan Stanley conference were the clearest public signal yet that Intel Foundry sees packaging as a major revenue opportunity.

## What is Nvidia's Rubin Ultra and why does it stress packaging?

Nvidia's **Rubin Ultra** is reportedly a chip so large it requires four reticle-sized compute dies stitched together into one package. That scale makes the packaging architecture a central engineering and cost challenge, not just a manufacturing detail.

The reported warpage problem on the four-die package illustrates how difficult this gets at scale. TSMC is said to be exploring CoPoS (panel-level packaging) as one potential solution, with a 2+2 die configuration as a possible fallback.

Nvidia's need for packaging capacity at this scale is part of what opens the door for Intel EMIB as an alternative supplier. The [Taiwan Super Micro](/articles/taiwan-super-micro-nvidia-chip-raid) supply chain story shows how tightly Nvidia's hardware ecosystem is scrutinized.

## Why are materials also becoming a bottleneck?

Packaging is not the only constraint. SemiAnalysis noted on Threads that one of the most underappreciated angles on the AI semiconductor buildout is materials — not just chips or fab equipment, but the critical materials that make modern chips possible.

A separate thread flagged China's indium phosphide controls as a hidden materials story inside AI infrastructure. AI data centers increasingly depend on compound semiconductors inside optical interconnects. The [data center optics](/articles/mesh-optical-technologies-50m-series-a) supply chain is one area where materials constraints are already visible.

Applied Materials also unveiled new 3D chipmaking and hybrid bonding systems aimed at scaling AI hardware, with executives from Nvidia, Intel, and Samsung focusing on advanced packaging — chiplets and 3D stacking — as the next performance lever at a VLSI panel.

This materials pressure connects to broader [AI memory supercycle](/articles/micron-ai-memory-supercycle-2030) dynamics that are reshaping semiconductor supply chains through the end of the decade.

## What does this mean for Intel Foundry?

Intel Foundry has struggled to compete with TSMC on leading-edge logic. Packaging is a different competitive axis — and one where Intel has existing technology in EMIB.

Multiple outlets reported that Intel's EMIB was being evaluated for Nvidia's next-generation architecture. Intel CFO David Zinsner's March 2026 statement at the Morgan Stanley conference — that the packaging business was shaping up to be significantly larger than originally anticipated — is the most concrete public signal of that opportunity.

The [IBM nanostack](/articles/ibm-nanostack-07nm-chip-density) work on chip density shows that multiple companies are pursuing different paths to push beyond the reticle limit.

The confirmed next milestone: Intel's packaging business trajectory, as described by CFO David Zinsner at the Morgan Stanley conference in March 2026, with Nvidia's next-generation architecture evaluation still ongoing.

## Frequently asked questions

****What is Intel EMIB?****

EMIB stands for Embedded Multi-die Interconnect Bridge. It is Intel's advanced packaging technology that connects multiple chips inside a single package. It is being evaluated as an alternative to TSMC's CoWoS for Nvidia's next-generation chip architecture, and Intel CFO David Zinsner said in March 2026 that the packaging business was shaping up to be significantly larger than originally anticipated.

****What is TSMC CoWoS and which chips use it?****

CoWoS, or Chip on Wafer on Substrate, is TSMC's advanced packaging technology and the current industry standard for high-performance AI chips. Nvidia's AI GPUs, AMD's accelerators, and Broadcom's custom ASICs are all packaged using CoWoS. Supply is constrained, with Nvidia absorbing a substantial portion of available capacity, leaving other customers struggling to secure allocation.

****Why is advanced packaging now the key battleground for AI chips?****

AI accelerators have grown so large they exceed the reticle limit — roughly 858 mm² — the maximum area a lithography stepper can pattern in one exposure. Once a chip requires multiple dies, packaging becomes the critical engineering and cost challenge. Nvidia's Blackwell already stitches two reticle-sized dies together, and Rubin Ultra reportedly requires four.

****What is Nvidia's Rubin Ultra packaging challenge?****

Nvidia's Rubin Ultra allegedly requires four reticle-sized compute dies stitched together into one package. There are reported rumors of a warpage problem on the four-die package. TSMC is said to be exploring panel-level packaging (CoPoS) as a potential solution, with a 2+2 die configuration as a possible fallback arrangement.

****Why are semiconductor materials becoming a supply chain concern for AI?****

Beyond chips and packaging, the materials that enable advanced semiconductors are also under pressure. SemiAnalysis flagged this as underappreciated. China's indium phosphide controls are one specific example — AI data centers depend on compound semiconductors in optical interconnects, and constraints on those materials can stall infrastructure buildout regardless of chip or packaging capacity.